Multiple history based micro partition prefetch optimization
US9569364B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2016 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Feb 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for prefetching cache lines. One technique includes dispatching a virtual processor and recording a first set of addresses associated with one or more cache lines used by the virtual processor. The technique also includes redispatching the virtual processor and recording a second set of addresses associated with one or more cache lines used by the virtual processor. The technique further includes comparing the first set of addresses with the second set of addresses to determine one or more common addresses between the first set and the second set. The technique includes placing the one or more common addresses into a memory. Finally, the technique includes redispatching the virtual processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.