Memory device, related method, and related electronic device
US9570115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Nov 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.