Managing skew in data signals
US9570128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2014 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Feb 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a signal that corresponds to a bit to be written to memory. The interface includes, for each line, circuitry for transmitting a bit to memory via the line, and a data de-skewer. For each line, the de-skewer receives a first data signal that represents a bit to be written. Each line has an inherent skew. The de-skewer generates a second data signal by applying a skew to the first. A selected extent of skew increases a likelihood of sampling the second data signal during a data-valid window thereof. The same de-skewer receives and skews a first data bit read from the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.