Semiconductor devices having through electrodes capped with self-aligned protection layers
US9570377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Apr 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices having through electrodes capped with self-aligned protection layers. The semiconductor device comprises a semiconductor substrate including an integrated circuit formed therein, an interlayer dielectric layer on the semiconductor substrate to cover the integrated circuit, an intermetal dielectric layer having at least one metal line that is provided on the interlayer dielectric layer and is electrically connected to integrated circuit, and a through electrode that vertically penetrates the interlayer dielectric layer and the semiconductor substrate. The through electrode includes a top portion that is capped with a first protection layer capable of preventing a constituent of the through electrode from being diffused away from the through electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.