Tiled hybrid array and method of forming
US9570428B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2016 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Jan 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/0364
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A tiled array of hybrid assemblies and a method of forming such an array enables the assemblies to be placed close together. Each assembly comprises first and second dies, with the second die mounted on and interconnected with the first die. Each vertical edge of a second die which is to be located adjacent to a vertical edge of another second die in the tiled array is etched such that the etched edge is aligned with a vertical edge of the first die. Indium bumps are deposited on a baseplate where the hybrid assemblies are to be mounted, and the assemblies are mounted onto respective indium bumps using a hybridizing machine, enabling the assemblies to be placed close together, preferably ≦10 μm. The first and second dies may be, for example. a detector and a readout IC, or an array of LEDs and a read-in IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.