Array substrate, manufacturing method thereof and display device
US9570473B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | May 26, 2014 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | May 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/133345
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate, a manufacturing method thereof and a display device are disclosed. The manufacturing method of an array substrate including: forming patterns including a thin film transistor, a gate wiring and a data wiring on the base substrate; the gate wiring and the data wiring are located in a PAD area; forming patterns of an insulating spacing layer, a first transparent electrode and a passivation layer, and forming a first via hole and a second via hole in areas corresponding to the gate wiring and the data wiring respectively to expose the gate wiring and the data wiring; a thickness of the insulating spacing layer in the PAD area on the array substrate is less than that of the insulating spacing layer in other areas. Therefore, the connection electrode can make better contact with the corresponding signal lines to avoid abnormal rubbing mura.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.