Array substrate and manufacture method thereof
US9570475B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 26, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Jun 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure provide an array substrate and a manufacture method thereof. The array substrate comprises a display region and a non-display region, the display region comprises a transistor, the transistor comprises a source electrode, a drain electrode and an active layer, the source electrode and the drain electrode are provided on the active layer and are respectively provided at two ends of the active layer. The non-display region is provided with an alignment mark, the alignment mark is provided in a same layer as the active layer and is configured for aligning the source electrode and the drain electrode with the active layer in the case of re-fabricating the source electrode and the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.