Thin film transistor array panel and manufacturing method of the same
US9570477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2016 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Feb 11, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136222
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.