TFT substrate manufacturing method and TFT substrate
US9570618B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Aug 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0223
Abstract
The present invention provides a TFT substrate manufacturing method and a TFT substrate. The TFT substrate manufacturing method of the present invention applies etching to source and drain contact zones of an active layer to have heights thereof lower than a height of a channel zone in the middle and configures the source and drain contact zones in a stepwise form so that charge carriers are affected by an electric field (Vds electric field) that is deviated in a direction away from a poly-silicon/gate insulation layer interface and the migration path thereof is caused to shift away from the poly-silicon/gate insulation layer interface thereby reducing the injection of high energy carriers into the gate insulation layer. Further, due to the formation of the steps in the drain contact zone, the peak intensity of the lateral electric field (Vds electric field) around the drain contact zone and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact zone are both reduced, making a pinch-off point shifted toward an edge of the drain contact zone, reducing drifting of threshold voltage, and improving TFT reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.