Efficient skew scheduling methodology for performance and low power of a clock-mesh implementation
US9571074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Jul 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to one aspect, a method may include receiving a circuit model that includes a clock mesh that controls each of a plurality of logic circuits by inputting a respective clock signal to an end-point of each logic circuit. The method may include providing an incremental latency adjustment to the circuit model by determining one or more end-points that are candidates for adjustment of a respective end-point's clock skew schedule. And, for each end-point that is associated with a negative front slack, adjusting a clock skew schedule of an end-point by a quantized amount. Further, for each end-point that is associated with a negative back-slack, adjusting the clock skew schedule of an end-point that is associated by a quantized amount. The method may also include repeating, the step of providing an incremental timing update. The method may include performing a timing evaluation upon the circuit model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.