Convolution-encoded hyper-speed channel with robust trellis error-correction
US9571126B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Apr 11, 2016 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Apr 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method, system, and computer program product for performing robust, parallel data transfer by a processor device. Data is segmented into k-bit segments, where k≧1. The k-bit segments are convolution encoded, using m≧1 stages of delay. The n output streams are transmitted in parallel for increased effective data rate, where n>k. The n output streams are received. An XOR (Exclusive OR) logic is applied to the n output streams with pathing allowed by the convolution encoding, in a trellis-decoding diagram.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.