Integrated circuit incorporating a low power data retiming circuit
US9571263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Jun 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0332
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A low power data retiming circuit incorporates CMOS components in certain sections that operate at a lower frequency in comparison to certain other sections that use components based on bipolar technology for operating at a relatively higher frequency. The data retiming circuit includes a clock recovery circuit wherein a voltage controlled oscillator provides a recovered clock to a clock generator circuit for generating a latched clock that is provided to a phase detector and a data serializer. The data serializer operates as a synchronous multiplexer for generating a retimed data output signal from a pair of latched data input signals. The phase detector and the data serializer operate in a half-rate mode wherein high and low voltage levels of the latched clock are used for clocking data. The half-rate mode of operation permits the use of a clock frequency that is half that of an input data rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.