Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping
US9575119B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2016 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Feb 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31922
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.