Digital signal processing data transfer
US9575900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Feb 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/251
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.