Moisture barrier for semiconductor structures with stress relief
US9576920B2 · kind B2 · utility
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28Claims
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Key dates
| Filing date | Jul 25, 2016 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Jul 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/36
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier layer is disposed over the substrate and between the substrate and the electrically conductive layer. A dielectric layer is disposed over the moisture barrier layer. The dielectric layer has an elastic modulus that is lower than an elastic modulus of the moisture barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.