Thin film transistor array panel and conducting structure
US9576984B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2016 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Mar 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.