Semiconductor device having stressor and method of forming the same
US9577097B2 · kind B2 · utility
4Cited by
8References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 23, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Jul 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
Abstract
A semiconductor device having a stressor is provided. A first trench and a second trench spaced apart from each other are formed in a substrate. A channel area is defined between the first trench and the second trench. A gate dielectric layer is formed on the channel area. A gate electrode is formed on the gate dielectric layer. The stressor includes a plurality of semiconductor layers formed in the first trench and the second trench and a plurality of interlayers formed between the semiconductor layers. Sidewalls of the first trench and the second trench are v-shaped (e.g., have a < or > shape).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.