System and method for fabricating super conducting circuitry on both sides of an ultra-thin layer

US9577177B1 · kind B1 · utility

Assignee

• The United States of America as represented by the Administrator of the National Aeronautics and Space Administration · US

Inventors

• Ari D. Brown · Ellicott City, US
• Vilem Mikula · Hyattsville, US

Key dates

• Filing date: May 25, 2016
• Grant date: Feb 21, 2017
• Expiry date: May 25, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76891
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.