Level shifter
US9577616B2 · kind B2 · utility
4Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Jan 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An exemplary level shifter includes a clock level shifter configured to generate a level shifted clock signal from an input clock signal; and a switched capacitor logic controller coupled to the clock level shifter. The switched capacitor logic controller is configured to steer the level shifted clock signal based on a data signal and the input clock signal, providing a level shifted version of the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.