Patent · US Active

Clock-gating cell with low area, low power, and low setup time

US9577635B2 · kind B2 · utility

8Cited by

9References

29Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Seid Hadi Rasouli · San Diego, US
Steven James Dillen · San Diego, US
Animesh Datta · San Diego, US

Key dates

Filing date	Jan 15, 2015
Grant date	Feb 21, 2017
Priority date	—
Expiry date	Jan 15, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH03K17/6872
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.