Method and apparatus for excess loop delay compensation in continuous-time sigma-delta analog-to-digital converters
US9577662B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2015 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Nov 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/426
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.