Algorithm to achieve optimal layout of decision logic elements for programmable network devices
US9582251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2015 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Mar 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.