Instruction set to enable efficient implementation of fixed point fast fourier transform (FFT) algorithms
US9582473B1 · kind B1 · utility
0Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2014 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Jan 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method and system for providing a Fast Fourier Transform (FFT) capability to a fixed point processor architecture is disclosed. In a first aspect the computer implemented method and system comprises providing an instruction set within the fixed point architecture. The instruction set includes a plurality of instructions to calculate at least one set of add operations within a FFT butterfly. The plurality of instructions are controlled by a mode register, wherein a plurality of vector register files and a scratch state memory provide input data to at the at least one set of add operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.