Patent · US Active

Test bench transaction synchronization in a debugging environment

US9582625B2 · kind B2 · utility

1Cited by

9References

39Claims

0Family size

Assignee

MENTOR GRAPHICS CORPORATION · US

Inventors

Badruddin Agarwala · Pleasanton, US
Tarak Parikh · San Jose, US
Vivek Bhat · San Jose, US
Neeraj Joshi · Morrisville, US

Key dates

Filing date	Jun 21, 2013
Grant date	Feb 28, 2017
Priority date	—
Expiry date	Dec 22, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/33
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

This application discloses a design verification tool to simulate a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design. The design verification tool can determine whether the simulated output for the circuit design is different than an expected output for the circuit design. A debug tool can synchronize the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.