Display driving circuit for eliminating delay errors among display driving signals, driving method thereof and display apparatus
US9583058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2014 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Sep 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Provided are a display driving circuit, a driving method thereof and a display apparatus. The display driving circuit comprises a timing sequence control unit (20) and at least one signal driving unit (30) connected to the timing sequence control unit (20). The timing sequence control unit (20) comprises a receiving module (201), a processing module (202) and a sending module (203). The receiving module (201) receives feedback signals (FB) outputted from respective signal driving units (30) to the timing sequence control unit (20); the processing module (202) obtains a maximum delay time after comparing signal delay time of the signal driving units (30) according to the feedback signals (FB); the sending module (203) sends a second clock signal (CLK2) to respective signal driving units (30) according to the maximum delay time such that respective signal driving units (30) receive the second clock signal (CLK2) simultaneously. Therefore, delay errors of the display driving signals can be eliminated, and distortion of the display image can be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.