Solder fatigue arrest for wafer level package

US9583425B2 · kind B2 · utility

Assignee

• Maxim Integrated Products, Inc. · US

Inventors

• Yong Li Xu · Phoenix, US
• Tiao Zhou · Irving, US
• Xiansong Chen · Allen, US
• Kaysar Rahim · Irving, US
• Viren Khandekar · Flower Mound, US
• Yi-Sheng Anthony Sun · Singapore, SG
• Arkadii V. Samoilov · Saratoga, US

Key dates

• Filing date: Jun 28, 2013
• Grant date: Feb 28, 2017
• Expiry date: Oct 12, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3841
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.