Compact design of scan latch
US9584121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2015 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Jun 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.