Structure of multi-mode supported and configurable six-input LUT, and FPGA device
US9584128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2014 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Jan 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17758
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A structure of a multi-mode supported and configurable six-input look-up table (LUT), and a field-programmable gate array (FPGA) device. The six-input LUT has six signal input ends and two signal output ends. The six-input LUT includes: a first five-input LUT, a second five-input LUT, a first multiplexer, and a second multiplexer. The first five-input LUT outputs a first output signal according to five data signals input by five signal input ends of the six-input LUT, where the first output signal is output by a first signal output end of the six-input LUT; the second five-input LUT outputs a second output signal according to the five data signals input by the five signal input ends of the six-input LUT; and the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.