Phase locked loop with accurate alignment among output clocks
US9584138B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Apr 5, 2016 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Apr 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0069
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.