Unified H-encoder for a class of multi-rate LDPC codes
US9584158B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 24, 2015 |
| Grant date | Feb 28, 2017 |
| Priority date | — |
| Expiry date | Jul 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6393
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A quasi-cyclic LDPC encoding apparatus is disclosed wherein a matrix H of the form [0 T; D E] is used, where T is a triangular matrix and D and E are arbitrary matrices selected to improve encoding performance. T and E vary with the size of an encoded data word whereas D is maintained constant. T and E are sparse such that encoding operations performed on them are computationally simple. Likewise D and its inverse are constant and pre-computed further reducing computation. T, E, and D and the inverse of D may be constrained to be quasi-cyclic, which reduces storage required to represent them and enables the performance of encoding operations using shift registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.