Unit-level formal verification for vehicular software systems
US9588877B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2016 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Mar 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.