Adaptive address translation method for high bandwidth and low IR concurrently and memory controller using the same
US9588880B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | May 26, 2011 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Apr 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adaptive memory address translation method includes the following steps. Multiple request instructions are received. A memory address corresponding to each request instruction includes a bank address. The memory addresses corresponding to the request instructions are translated, such that the bank addresses corresponding to at least one part of the any two adjacent request instructions are different. A numerical translation is utilized to translate the memory addresses corresponding to the request instructions, such that the memory addresses corresponding to the any two adjacent request instructions have less different bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.