Memory circuit using resistive random access memory arrays in a secure element
US9588908B2 · kind B2 · utility
19Cited by
36References
15Claims
0Family size
Inventor
Key dates
| Filing date | Sep 29, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Oct 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit using resistive random access memory (ReRAM) arrays in a secure element. The ReRAM arrays can be configured as content addressable memories (CAMs) or random access memories (RAMs) on the same die, with the control circuitry for performing comparisons of reference patterns and input patterns located outside of the ReRAM arrays. By having ReRAM arrays configured as CAMs and RAMs on the same die, certain reference patterns can be stored in CAMs and others in RAMs depending on security needs. For additional security, a heater can be used to erase reference patterns in the ReRAM arrays when desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.