Flow pinning in a server on a chip
US9588923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2014 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Mar 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.