Exploiting frame-to-frame coherence for optimizing color buffer clear performance in graphics processing units
US9589312B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2014 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Feb 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is described for dynamically optimizing color buffer clear performance in graphics processing units. A method of embodiments, as described herein, includes allocating and initializing a first set of control bits associated with a framebuffer in a graphics processing unit (GPU), and rendering a first frame, wherein the first set of control bits are associated with the first frame. The method may further include allocating a second set of control bits associated with a second frame, and rendering the second frame. The method may further include facilitating an expedited resolve operation of the second frame based on a frame-to-frame coherence associated with the first and second frames.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.