Handling maximum activation count limit and target row refresh in DDR4 SDRAM
US9589606B2 · kind B2 · utility
14Cited by
1References
20Claims
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Key dates
| Filing date | Dec 4, 2014 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Apr 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40603
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Efficiently tracking activations to rows of memory using a reduced number of row activation counters that indicate whether a memory row is activated during an activation period and row activation counters that indicate a number of permitted activations to a memory row within a maximum activation window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.