Multi-chip memory system having chip enable function
US9589614B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Oct 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device includes first and second nonvolatile memory groups that respectively include first and second nonvolatile memory chips, a memory controller connected to the first and second nonvolatile memory groups in common through input/output lines and at least one control line, and a group select circuit connected to the memory controller through the at least one control line and chip enable lines. The group select circuit is connected to the first and second nonvolatile memory groups through a plurality of first and second chip enable lines, respectively. The group select circuit, in response to receiving a control signal through the at least one control line, is configured to transmit chip enable signals to a selected memory group among the first nonvolatile memory group and the second nonvolatile memory group through selected chip enable lines among the first chip enable lines and the second chip enable lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.