Single-ended memory signal equalization at power up
US9589626B1 · kind B1 · utility
11Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2016 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Jan 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus having a first circuit and a second circuit. The first circuit may be configured to buffer an input signal received as a single-ended signal from a data bus connected between a memory channel and a memory controller. The second circuit may be configured to condition the input signal relative to a reference voltage to generate a differential signal. The reference voltage may be isolated from the second circuit in response to a transition from a power down condition to a power on condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.