Methods and devices for a DDR memory driver using a voltage translation capacitor
US9589627B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2016 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | May 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation capacitor. One embodiment is high speed level translation memory driver apparatus comprising a plurality of field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) logic gates to drive the FETs, and a voltage translation capacitor with a first terminal of the voltage translation capacitor connected to an output of a second CMOS logic gate and a second terminal of the voltage translation capacitor connected to a gate terminal of a first P-type FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.