Semiconductor memory device and controlling method thereof
US9589651B1 · kind B1 · utility
3Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2016 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Mar 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of charge accumulation type memory cells; and a control unit that controls the memory cell array. The control unit, when executing an erase operation on the memory cell array, applies an erase voltage to the memory cells. The erase voltage is a voltage in a pulse form. The control unit performs control that, compared to when the erase operation is in a first stage, increases a voltage value and shortens a pulse width of the erase voltage when the erase operation is in a second stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.