Patent · US Active

Chip package

US9589920B2 · kind B2 · utility

10Cited by
0References
31Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 26, 2015
Grant dateMar 7, 2017
Priority date
Expiry dateAug 26, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/37001
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An embedded die package and method of manufacture, the die package comprising a die having I/O contact pads in a passivation layer wherein the die contact pads are coupled to a first side of a feature layer by an adhesion/barrier layer, and a layer of pillars extends from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material and wherein the feature layer comprises routing lines that are individually drawn by laser exposure of photoresist under guidance of an optical imaging system for good alignment with both the I/O contact pads of the die and with the subsequently to be deposited pillars that are positioned with respect to the package edges.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.