Method of manufacturing semiconductor device
US9589923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Aug 31, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.