Anti-fuse one-time programmable memory cell and anti-fuse one-time programmable memory array
US9589971B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2016 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Sep 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/235
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An anti-fuse memory cell is provided. The anti-fuse memory cell includes a programmable transistor and a selection transistor. The programmable transistor includes a gate structure, a first doped region and a lightly doped region. The first doped region is divided into a first portion doped region, a second portion doped region and a third portion doped region. The first and second portion doped regions are respectively a source and a drain of the programmable transistor, and the third portion doped region is disposed between the first and second portion doped regions. The lightly doped region is distributed around a channel region of the programmable transistor, and adjacent to the first, second and third portion doped regions. The selection transistor includes a gate structure and a second doped region, and connected in series to the programmable transistor through the first portion doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.