Methods of forming semiconductor devices to include single body interconnection patterns using fine patterning techniques, and semiconductor device so formed
US9590034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Apr 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming fine patterns for a semiconductor device includes providing a substrate with a first region and a second region, forming a conductive layer on the substrate, the conductive layer including a plate portion covering the first region and first protruding portions extending from the plate portion in a first direction and covering a portion of the second region, forming first mask patterns on the conductive layer, the first mask patterns extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, forming a second mask pattern on the second region to cover the first protruding portions, and patterning the conductive layer using the first and second mask patterns as an etch mask to form conductive patterns. In plan view, each of the first protruding portions is overlapped with a corresponding one of the first mask patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.