Carry-skip one-bit full adder and FPGA device
US9590633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2014 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Jan 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1733
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A carry-skip one-bit full adder and a field programmable gate array device, the full adder includes: a first multiplexer, a second multiplexer, and an adder, the first multiplexer includes a first addend input end and a first constant input end configured to input a first constant to the first multiplexer; the second multiplexer includes a second addend input end and a second constant input end configured to input a second constant to the second multiplexer; when the first addend input end is not used for input of a first addend, and/or when the second addend input end is not used for input of a second addend, the first multiplexer selects to output the first constant input, and the second multiplexer selects to output the second constant input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.