High-speed programmable frequency divider with 50% output duty cycle
US9590637B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Aug 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider includes a multiplexer having a first input terminal coupled to receive a first value M and a second input terminal for receiving a second value that is M+LSB, the multiplexer is configured to alternately output the first value M and the second value. The frequency divider includes a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles. A divide-by-two counter having an input coupled to the output of the multi-modulus divider, is operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency of N, where N is equal to 2M+LSB. Duty cycle correction logic is coupled to the output of the divide-by-two counter and is configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when N is odd.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.