Phase error detection in phase lock loop and delay lock loop devices
US9590643B2 · kind B2 · utility
1Cited by
63References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 13, 2015 |
| Grant date | Mar 7, 2017 |
| Priority date | — |
| Expiry date | Nov 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.