Interface between a bus and a inter-thread interconnect
US9594720B2 · kind B2 · utility
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Key dates
| Filing date | Oct 21, 2013 |
| Grant date | Mar 14, 2017 |
| Priority date | — |
| Expiry date | Oct 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17356
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing apparatus comprising: a bus; a first processor connected to the bus and configured to communicate over the bus according to a bus protocol; a second, multithread processor; and an inter-thread interconnect based on a system of channels. The apparatus also comprises an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side for interfacing with the system of channels. The first processor is thereby operable to communicate with a designated one of said threads via the bus and a respective channel of the inter-thread interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.