Method and apparatus for mitigation of packet delay variation
US9596072B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2014 |
| Grant date | Mar 14, 2017 |
| Priority date | — |
| Expiry date | Apr 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/283
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus for mitigation of packet delay variation, PDV, in a packet-based network, comprising an ingress port to receive event messages, each message being timestamped with a local ingress timestamp at the instant of reception of the message using a local internal clock; an extraction unit to extract a timestamp embedded in the received message; a computation unit to calculate a time offset between the extracted embedded timestamp and the local ingress timestamp of the received event message to record the calculated time offset as a maximum observed delay, if the calculated time offset exceeds a previously recorded maximum observed delay, the computation unit adjusting an internal transmission delay time before onward transmission of the event message from an egress port depending on a time difference between recorded maximum observed delay and calculated time offset of the event message to minimize the packet delay variation, PDV, at the egress port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.