Testing device for validating stacked semiconductor devices
US9599661B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2012 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | Aug 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2889
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Embodiments of the invention describe apparatuses, systems and method for utilizing testing instruments having electrical interconnects formed from High Density Interconnect (HDI) multi-layer substrates. Electrical signals may be routed between devices mounted on HDI substrates by way of conductive interconnects formed within their multiple layers. The conductive interconnects are generally comprised of metal interconnects and vias, where each via penetrates between layers to couple a metal interconnect from one layer to a metal interconnect from another layer. By utilizing HDI substrates, embodiments of the invention enable “breaking out” the signal pins on multiple layers, perhaps double or triple the routing layers of the package channel; however, the geometry of the transmission lines and other factors may be chosen to ensure channel parameters such as impedance and crosstalk closely emulate the final device package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.